SystemVerilog/UVM Verification Engineer for ASIC (Vancouver)

SystemVerilog/UVM Verification Engineer for ASIC (Vancouver)

14 Oct
|
Qualcomm
|
Vancouver

14 Oct

Qualcomm

Vancouver

Qualcomm Canada ULC is seeking an ASIC verification engineer to contribute to the complete verification lifecycle, from system-level concept to tape-out. The role focuses on pre-silicon test planning, testbench development, and property checking using SystemVerilog-UVM.

Applicants should have a bachelor’s or higher in Engineering/Science and 2+ years of ASIC experience. A Master’s or PhD is preferred for more senior paths within the group.

📌 SystemVerilog/UVM Verification Engineer for ASIC (Vancouver)
🏢 Qualcomm
📍 Vancouver

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