Elevate your career with Ciena as an ASIC Synthesis Engineer. Shape high-speed networking solutions while executing critical front-end implementation tasks in a collaborative, diverse setting.
Ciena seeks an ASIC Synthesis Engineer to drive frontend implementation of cutting-edge ASIC technology. This role involves synthesis, static timing analysis, and clock domain validation that are vital for Ciena's optical networking solutions. Candidates should possess knowledge in the ASIC development process and have a strong grasp of logical equivalence checking and timing constraints.
Key Responsibilities:
• Execute frontend implementation for assigned IP subsystems
• Develop timing constraints for synthesis and signoff
• Perform logical equivalence verification during pre/postlayout stages
• Validate clock domain crossings for ASIC integration
• Create and optimize scripts enhancing workflows
Requirements:
• B.Sc. in Electrical/Computer Engineering or related field
• Knowledge of ASIC implementation flows
• Familiarity with RTL design principles
• Ability to work within multidisciplinary teams
• Experience in managing project deliverables
Contribute your expertise to high-performance optical networking at Ciena, making an impactful difference.
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