As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We're a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being-on and off the job.

At Ciena, we are at the forefront of the telecommunications industry, and our Wavelogic modem family of products plays a crucial role in our success. As a Digital Verification Engineer (FEC), you will be an integral part of a team responsible for implementing cutting-edge verification strategies in order to thoroughly simulate and validate functional blocks and subsystems for Ciena's Forward Error Correction (FEC) IP. Reporting to the ASIC Senior Manager, you will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects to simulate and validate functional blocks and subsystems.

Read and understand the FEC architecture and functional requirements specification document(s) and communicate and collaborate with FEC designers, DSP modelers, FEC verifiers, systems engineers and architects. You will be responsible for developing verification, functional coverage and formal verification test plans. Thoroughly validate one or more architectural FEC functional blocks using a combination of simulation, formal, and coverage methods.

Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and C++. Provide status updates on verification progress on a regular basis and communicate risks as needed.



Mentor and supervise junior verification engineers requiring robust understanding of team outputs to foster peers' technical and professional growth.

Excellent communication and interpersonal skills with demonstrated ability to convey complex technical concepts clearly and effectively influence stakeholders.

Minimum

Bachelor's degree in Electrical, Computer or Software Engineering. ~ Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors. ~ Proven ability to determine comprehensive digital verification and coverage strategies. ~ Proven ability to foster a culture of innovation and continuous improvement within the team via demonstrated leadership and communication capabilities. ~ Assets Strong background in Forward Error Correction (FEC) and/or DSP.

Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++. Proficiency in bug tracking using Jira and source code management and revision tracking using GIT. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission.

In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

Equal Opportunity and Diversity Ciena values the diversity of its workforce and respects its employees as individuals. Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

📌 Principal/Team Lead, Digital Verification Engineer (FEC) (Ottawa)
🏢 Ciena
📍 Ottawa