Drive innovation in ASIC Physical Design with Synopsys. As a Senior Engineer, you'll lead complex SoC implementations and optimize design flows for cutting-edge test chips. At Synopsys, we’re seeking an experienced ASIC Physical Design Engineer with over nine years of expertise.
In this senior role, you will contribute to physical design implementations across DDR, HBM, and UCIe protocols. You will be instrumental in floor planning, optimizing the RTL-to-GDS flow, and ensuring design reliability through thorough static timing analysis. Key Responsibilities:
- Implement physical design for test chips across key protocols
- Develop tailored floorplan and power strategies
- Optimize RTL-to-GDSII flow for performance
- Execute static timing and physical verifications
- Integrate updated covercells and manage QA of macros Requirements:
- 9+ years in ASIC physical design experience
- Expertise in ASIC physical design flow
- Familiarity with IP integration methodologies
- Proficiency in state-of-the-art CAD tools
- Experience in leading cross-functional projects Leverage your design expertise and creative thinking to enhance Synopsys's high-quality IP solutions.