Take charge as a Senior Verification Manager at Synopsys, where you will oversee SERDES PHY mixed-signal verification. Optimize your team's capabilities for high-impact silicon projects.In this leadership role, you will manage verification staff engaged in mixed-signal design challenges. Your expertise will be crucial in debugging complex issues, assessing coverage, and ensuring the sign-off quality of SERDES PHY IPs. You'll play a pivotal role in cross-disciplinary engagement to close technical gaps.Key Responsibilities:Lead verification efforts in mixed-signal environments using UVMTroubleshoot customer escalations and debug priority regressionsMaintain rigorous standards for verification qualityDefine co-simulation methodology and standardsFacilitate collaboration with analog and firmware teamsRequirements:10+ years in ASIC verification with a focus on mixed-signal3+ years leading verification engineersExpertise in PCIe and Ethernet SERDESProficient in SystemVerilog and verification methodologiesStrong scripting ability using Python or PerlContribute to cutting-edge verification processes while building a technically skilled team at Synopsys.

📌 Senior Verification Manager With Serdes Focus (Mississauga)
🏢 Synopsys
📍 Mississauga