Join a dynamic team as an ASIC Design Verification Engineer focused on Machine Learning technologies. Utilize your expertise in UVM and System Verilog to shape next-generation hardware solutions.
In this role, you will be engaged in creating verification strategies and test plans for advanced ML designs. Collaboration with architects and design leads is crucial, as is your ability to swiftly adapt to evolving specs and standards. Your robust background in digital design concepts and various bus protocols will enhance team productivity and drive innovative verification methodologies.
Key Responsibilities:
• Develop IP verification strategy and test plans
• Create verification environments with UVM/System Verilog
• Identify and resolve design verification challenges
• Perform RTL and functional coverage analyses
• Communicate deviations from established plans efficiently
Requirements:
• Bachelor's degree in Engineering or related field
• Proficient in UVM and System Verilog
• Scripting experience in Perl and Python
• Understanding of AHB/AXI bus protocols
• Strong problem-solving and communication skills
Utilize your skills in digital design and verification to make impactful contributions to hardware innovations that improve everyday life.
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