Lead ASIC Design-for-Test implementation for Cisco Silicon One, applying scan insertion, ATPG, and gate-level simulation expertise to networking chips. As an ASIC Implementation Technical Lead, you will work across front-end RTL and backend physical design teams. You will understand chip architecture, drive DFT requirements early, and contribute to next-generation networking chips. The work spans implementation flow, quality processes, post-silicon validation, and selected physical design signoff activities. Key Responsibilities:
Drive DFT requirements with front-end RTL and physical design teams Lead DFT and quality processes through implementation flow Support post-silicon validation and debug phases Contribute to next-generation networking chip development Provide exposure to physical design signoff activities Requirements:
Bachelor’s degree and eight-plus years of ASIC Design experience Master’s degree and six-plus years of ASIC Design experience Prior scan insertion and ATPG experience using Tessent tool sets Gate-level SDF simulation and VCS debugging experience Post-silicon validation and ATE pattern translation experience Apply ASIC implementation, DFT, ATPG, and validation expertise to Cisco Silicon One networking silicon development.