Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You understand that the real challenge in mixed-signal verification is not running simulations, it is building environments where analog and digital worlds talk to each other without breaking. You are comfortable reading a schematic, understanding such as ADC, AFE, PLL is supposed to do, and then building the test bench that proves it does it under every corner case that matters. Define and execute verification test plans for Ethernet and PCIe SERDES IP, tracking coverage metrics and ensuring completeness across functional, analog, and mixed-signal scenarios

Verify SERDES subsystems including TX/RX datapaths, equalization algorithms, CDR loops, PLL locking behavior, and analog-digital interface interactions across process corners and operating conditions

Debug simulation failures that span analog, digital, and mixed-signal domains using tools like HSPICE, XA, CustomSim, and VCS

Perform design reliability checks including electromigration, IR drop analysis, and device-level stress evaluations to ensure robustness in production silicon

Collaborate with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to align verification strategies with IP requirements and silicon timelines

Develop Python, Perl, and shell-based automation to improve simulation throughput, regression efficiency, and debug workflows





Deliver verified IP that ships in high-volume production SoCs powering AI, automotive, cloud, and mobile applications

Catch critical analog-digital interaction bugs before tapeout, directly preventing silicon respins and saving months of schedule and millions in cost

Define verification methodologies that become the standard across Synopsys IPG teams, influencing how mixed-signal IP is verified company-wide

Enable first-pass silicon success for SERDES products deployed in top-tier customer designs, strengthening Synopsys reputation and customer trust

Mentor junior engineers and new graduates, raising the technical capability of the team and building institutional knowledge in AMS verification

Drive improvements in coverage metrics, simulation performance, and debug efficiency that make the entire verification flow more predictable and scalable

Bachelor's degree with 5 years’ relevant experience or Master's degree with minimum of 3 years of relevant experience (Electrical Engineering, Computer Engineering, or related field.

Proficiency with System Verilog and UVM for digital and mixed-signal testbench development

Experience with AMS simulation tools such as HSPICE, XA, CustomSim, or VCS AMS (for senior candidates, hands-on experience required; for new graduates, coursework or project exposure is sufficient)

Solid scripting skills in Python, Perl,



or UNIX shell for automation and productivity improvements For senior-level candidates, demonstrated experience in AMS co-simulation, SERDES verification, or behavioral modeling with a track record of owning verification flows and debugging complex analog-digital interactions

Experience with design reliability analysis including EM/IR checks is a plus

You do not wait for perfect documentation or complete specs, you ask the designer the right questions, build a test plan from what you know, and refine it as you learn more

You can explain a complex analog-digital interaction to a digital verification engineer or a coverage gap to an analog designer without losing either of them in jargon

You push back when a test plan is too shallow or a coverage metric does not actually prove what it claims to prove, and you do it constructively

You are comfortable mentoring others, whether that is walking a current graduate through their first UVM testbench or helping a colleague debug a tricky PLL convergence issue

You will join the Synopsys IPG Co-Simulation team, a specialized group focused on verifying advanced Ethernet and PCIe SERDES IP used in top-tier SoCs across AI, automotive, cloud, and high-performance computing applications. The team collaborates closely with analog designers, digital verification engineers, modeling teams, and system architects across global Synopsys sites. This is a highly technical environment where AMS co-simulation expertise is valued, and where the verification work you do directly influence silicon success and customer deployments.

The team supports both new graduates and experienced engineers, with mentorship structures and growth paths calibrated to experience level.

📌 AMS Design Verification Engineer (Mississauga)
🏢 Synopsys
📍 Mississauga