Build RTL and verification expertise at Toronto-based StarIC, supporting hybrid digital IC development from modeling through gate-level simulation. Work across mixed-signal designs.
This senior engineering position covers digital blocks and ICs from initial concept, architecture, and specification through final verification. You will use VHDL or Verilog, front-end tools, simulators, synthesis, static timing analysis, back-annotation, and gate-level simulation. Responsibilities also include vector generation, lab testing, documentation, and incremental maintenance of digital designs, test systems, software, and scripts.

Key Responsibilities
Define architectures and specifications for digital IC blocksDevelop RTL models and verification environmentsPerform synthesis, timing closure,



and gate-level simulationGenerate vectors and support lab testingDocument designs and execute incremental maintenance updatesRequirements: BSc or MSc in Electronic Engineering or Computer EngineeringThree to six years of digital IC design experienceVHDL or Verilog design and simulation experienceSynopsys, Cadence, or Mentor front-end flow experienceHands-on csh, Tcl/Tk, or Perl scripting experienceBring RTL, verification, synthesis, simulation, and scripting capabilities to StarIC’s digital integrated circuit development work. #J-18808-Ljbffr

📌 Digital Electronics Verification Engineer I (Winnipeg)
🏢 StarIC
📍 Winnipeg