SystemVerilog and UVM expertise define this Senior SoC Verification Engineer role. Work independently on advanced SoCs using ASIC and FPGA technologies.
This senior individual contributor develops robust verification environments for complex digital ASICs and SoCs. You will create test strategies, execute plans, and support high-quality silicon and hardware solutions. Collaboration spans hardware, software, systems, suppliers, and technical experts.
Key Responsibilities:
- Develop and verify complex SoCs and digital ASIC designs
- Create protocol generators, traffic generators, checkers, and self-checking environments
- Develop and execute requirements-based comprehensive test plans
- Define block-level and sub-chip verification tests
- Support bring-up,
integration, debugging, and issue resolution
Requirements:
- Bachelor's degree in engineering, computer science, or related discipline
- Eight or more years of ASIC or SoC verification experience
- Advanced SystemVerilog and Python scripting proficiency
- Robust hands-on knowledge of UVM methodology
- Experience with SVA, coverage, and formal verification tools
Apply advanced SystemVerilog, UVM, coverage, and formal verification skills to complex SoC engineering projects.