Lead embedded memory compiler architecture at Silvaco using SRAM design and PPA optimization expertise across multiple process nodes. Serve customers globally.
Silvaco seeks a Memory Design Lead to direct architecture, circuit design, physical implementation, and delivery for its embedded memory compiler portfolio. You will guide SRAM, ROM, register file, and dual-port RAM development while translating SoC requirements into compiler specifications. The role combines technical leadership, customer engagement, silicon validation, and roadmap ownership.

Key Responsibilities
Lead memory compiler architecture, circuit design, and physical implementationOptimize Vmin, leakage, performance, area, and yield across PVT cornersSet portfolio roadmaps across variants, nodes, features, and methodologiesLead characterization, verification, signoff,



and silicon validation programsTranslate customer requirements into PPA commitments and compiler specificationsRequirements: BS, MS, or PhD in Electrical or Computer Engineering10+ years designing embedded memories with production SRAM tapeoutsExperience with FinFET or advanced sub-7nm process nodesExpertise in SPICE, Monte Carlo, Vmin, yield, and reliability analysisLeadership experience managing or technically leading six-plus memory designersApply memory design leadership, compiler architecture, and customer-facing PPA expertise to Silvaco’s embedded memory portfolio. #J-18808-Ljbffr

📌 Memory Design Lead Embedded Compiler (Winnipeg)
🏢 Silvaco
📍 Winnipeg