Drive SoC scan insertion and ATPG execution at AMD in Markham or Ottawa, applying DFT expertise to complex next-generation products.
This engineer implements, verifies, optimizes, and deploys advanced DFT solutions across complex SoCs. The work spans scan architectures, test compression, ATPG strategies, and ASIC development flows. Collaboration includes architecture, design, verification, physical design, CAD, and product engineering teams.
Key Responsibilities
Drive end-to-end SoC scan insertion and DFT implementationDevelop scan chains, compression, and ATPG strategiesAnalyze coverage and ATPG results to improve qualityDebug simulation, emulation, and full-chip integration issuesSupport silicon bring-up, yield improvement, and failure analysisRequirements:
Experience with scan insertion, ATPG, and DFT methodologiesStrong digital design and ASIC flow knowledgeExperience with hierarchical ATPG and test compressionFamiliarity with Verilog or SystemVerilog and scripting languagesBachelor’s or Master’s degree in Electrical or Computer EngineeringUse analytical debugging and team-oriented engineering skills to advance AMD DFT quality, coverage, manufacturability, and scalable test solutions.
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