Senior Asic Verification Engineer, Systemverilog/Uvm (Ottawa)

Senior Asic Verification Engineer, Systemverilog/Uvm (Ottawa)

13 Nov
|
Ciena Canada
|
Ottawa

13 Nov

Ciena Canada

Ottawa

Ciena Canada in Ottawa is seeking a Senior Digital ASIC Verification Engineer to lead verification of high‑speed, highly integrated digital ASICs, focusing on top‑level functionality, cross‑IP interactions and system‑level use cases.

You will own verification activities, develop SystemVerilog/UVM environments, create test scenarios, debug failures, and guide junior engineers while advancing verification methodology.

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📌 Senior Asic Verification Engineer, Systemverilog/Uvm (Ottawa)
🏢 Ciena Canada
📍 Ottawa

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