Drive SoC scan insertion and ATPG execution at AMD in Markham or Ottawa, applying DFT expertise to complex next-generation products.
This engineer implements, verifies, optimizes, and deploys advanced DFT solutions across complex SoCs. The work spans scan architectures, test compression, ATPG strategies, and ASIC development flows. Collaboration includes architecture, design, verification, physical design, CAD, and product engineering teams.
Key Responsibilities:
- Drive end-to-end SoC scan insertion and DFT implementation
- Develop scan chains, compression, and ATPG strategies
- Analyze coverage and ATPG results to improve quality
- Debug simulation, emulation, and full-chip integration issues
- Support silicon bring-up, yield improvement,
and failure analysis
Requirements:
- Experience with scan insertion, ATPG, and DFT methodologies
- Strong digital design and ASIC flow knowledge
- Experience with hierarchical ATPG and test compression
- Familiarity with Verilog or System Verilog and scripting languages
- Bachelor’s or Master’s degree in Electrical or Computer Engineering
Use analytical debugging and cooperative engineering skills to advance AMD DFT quality, coverage, manufacturability, and scalable test solutions.