Strong hands-on experience in RTL Design using Verilog/SystemVerilog.
Hands-on experience in PCIe
Positive understanding of digital design fundamentals, including: FSM design, Pipelining, Clock domain crossing (CDC), Reset architecture, Synchronizers, Low-power design concepts
Strong hands-on experience in RTL Design using Verilog/SystemVerilog.
Hands-on experience in verification of PCIe (Gen3/Gen4/Gen5) protocols.
Good understanding of digital design fundamentals, including: FSM design, Pipelining, Clock domain crossing (CDC), Reset architecture, Synchronizers, Low-power design concepts
Experience in micro-architecture development and RTL implementation.
Knowledge of synthesis constraints and timing concepts.
Familiarity with Lint, CDC, STA, and low-power verification methodologies.
Strong debugging and problem-solving skills.
📌 RTL Design Engineer (Canada)
🏢 Yochana IT
📍 Canada
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