Lead FEC verification at Ciena in Ottawa using SystemVerilog, UVM, C++, simulation, and formal methods. Apply deep expertise to Wavelogic modem products.

As a Principal Digital Verification Engineer, you will help validate functional blocks and subsystems for Ciena’s Forward Error Correction IP. You will collaborate with designers, DSP modelers, verifiers, systems engineers, and architects. The work supports comprehensive verification, functional coverage, and formal verification strategies for high-speed connectivity products.

Key Responsibilities:

- Develop verification, coverage, and formal verification test plans
- Validate FEC blocks using simulation, formal, and coverage methods
- Create SystemVerilog UVM and C++ testbench environments
- Monitor regressions, analyze coverage, and debug failures




- Mentor junior verification engineers and communicate progress

Requirements:
- Ten or more years of verification experience
- Bachelor’s degree in Electrical, Computer, or Software Engineering
- Significant experience with C/C++, SystemVerilog, UVM, SVA, and simulators
- Ability to define comprehensive digital verification and coverage strategies
- Solid decision-making, communication, leadership, and problem-solving skills

Bring principal-level verification leadership, FEC knowledge, and SystemVerilog expertise to Ciena’s Ottawa engineering team.

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📌 Principal Fec Digital Verification Engineer (Ottawa)
🏢 Ciena Canada
📍 Ottawa