Design next-generation power control systems at Qualcomm Canada ULC using Verilog, SystemVerilog, and advanced ASIC development practices.

This ASIC Digital Design Engineer develops complex RTL for high-performance, low-power products. The work spans architecture, microarchitecture, implementation, and subsystem integration across the VLSI development cycle. Collaboration includes verification, synthesis, physical design, DFT, systems, and software teams.

Key Responsibilities:
Develop digital designs using Verilog, VHDL, and SystemVerilog
Create microarchitecture for next-generation power control systems
Integrate complex subsystems into SoC designs
Coordinate with multisite leads across United States and India
Analyze reports and run ASIC development tools

Requirements:
Five to eight years of digital ASIC front-end design experience
Expertise with complex multi-clock and multi-power-domain RTL
Experience with UPF and power-domain crossing
Familiarity with AHB, AXI, SPMI, I2C, and SPI
Expertise in Perl and TCL languages

Apply ASIC design expertise, RTL development, and low-power methodology to Qualcomm power control systems.

📌 Asic Digital Design Engineer Markham (Canada)
🏢 Qualcomm
📍 Canada