Design complex digital integrated circuits in Burnaby using SystemVerilog and Verilog. Support ASIC validation, debugging, and implementation decisions.
As a Senior Engineer I-Design, you will contribute to Microchip’s Data Center Solutions business unit under experienced leaders. The work covers RTL design for blocks, subsystems, or devices ranging from 100K to 50M+ gates. You will collaborate with design, verification, architecture, and physical design teams on storage and computer interface products.
Key Responsibilities: Design digital integrated circuits using Verilog and SystemVerilog
Define features and document implementation details
Support emulation, ASIC validation, debugging, and workarounds
Resolve technical issues with distributed design and verification teams




Justify implementation decisions and trade-offs with architects
Requirements: Bachelor’s or master’s degree in electrical or computer engineering
Three to five years of related experience
Experience with complex ASIC design flows and RTL design
Knowledge of synthesis, static timing analysis, and physical design
Analytical, debugging, communication, teamwork, and time management skills
Apply digital design, ASIC flow, and debugging expertise to Microchip’s Data Center Solutions products in Burnaby.

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📌 Senior RTL Design Engineer (British Columbia)
🏢 Microchip Technology
📍 British Columbia