Lead embedded memory compiler architecture at Silvaco using SRAM design and PPA optimization expertise across multiple process nodes. Serve customers globally.
Silvaco seeks a Memory Design Lead to direct architecture, circuit design, physical implementation, and delivery for its embedded memory compiler portfolio. You will guide SRAM, ROM, register file, and dual-port RAM development while translating SoC requirements into compiler specifications. The role combines technical leadership, customer engagement, silicon validation, and roadmap ownership.
Key Responsibilities: Lead memory compiler architecture, circuit design, and physical implementation
Optimize Vmin, leakage, performance, area, and yield across PVT corners
Set portfolio roadmaps across variants, nodes, features, and methodologies
Lead characterization, verification, signoff,



and silicon validation programs
Translate customer requirements into PPA commitments and compiler specifications
Requirements: BS, MS, or PhD in Electrical or Computer Engineering
10+ years designing embedded memories with production SRAM tapeouts
Experience with FinFET or advanced sub-7nm process nodes
Expertise in SPICE, Monte Carlo, Vmin, yield, and reliability analysis
Leadership experience managing or technically leading six-plus memory designers
Apply memory design leadership, compiler architecture, and customer-facing PPA expertise to Silvaco’s embedded memory portfolio.

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📌 Memory Design Lead Embedded Compiler (Quebec City)
🏢 Silvaco
📍 Quebec City