AMD in Markham, ON seeks an experienced IC layout engineer to design digital/analog layouts from schematics using Cadence Virtuoso and leading foundry tech. You’ll handle floorplanning, routing, and tapeout tasks across multiple blocks with verification at all levels.
Knowledge of PLL/DLL/VCO, DACs and IP-style layouts is crucial. Ideal candidates have CMOS theory, 2nm/3nm exposure, scripting skills (Perl/TCL/SVRF/SKILL), and a track record with LVS/DRC/EMIR.