As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job.

We’re building the next generation of 448G electrical SerDes and pioneering optical IMDD systems to power tomorrow’s networks. Our engineering team lives at the intersection of high-performance DSP design, system modeling, and optical innovation. We are seeking a highly skilled Senior SerDes System/DSP Design Engineer to join our advanced engineering team .

In this role, you will lead the architecture, design, and validation of high-speed serial transceivers across electrical and optical domains. You will leverage your expertise in systems engineering, control theory, DSP algorithms, and modeling to develop cutting-edge serial electrical/optical-IMDD transceiver solutions. This position offers the opportunity to work on industry-leading designs at the intersection of electrical SerDes technology and advanced optical communications, driving innovations that enable next-generation high-capacity networks.

Lead the design and development of electrical SerDes DSP architectures for high-speed data communication systems. Perform system-level evaluation, modeling, and performance analysis of SerDes transceiver solutions including impairments and mitigation techniques. Integrate control theory and advanced DSP designs into feasible hardware implementations.

Collaborate with cross-functional teams (analog design, ASIC design, electro-optical hardware, firmware) to optimize SerDes performance in end-to-end systems. Conduct design trade-offs to meet stringent performance, power, and area targets. Analyze channel models,



analog circuits impairments (DAC, ADC, AFE, …) and system constraints to determine system level margin and FEC (forward error correction) performance and optimize system margin.

Document design specifications, system performance results, and contribute to IP generation and innovation roadmaps. Advanced expertise in electrical SerDes DSP design and implementation. Robust proficiency in control theory and digital signal processing (DSP) applied to high-speed communication systems.

Deep understanding of adaptive equalization techniques for high-speed links. Practical knowledge of FEC performance modeling and system-level performance optimization.

Experience with MATLAB, Python, or C/C++ for algorithm design and simulation. Strong problem-solving skills and ability to work across hardware/software boundaries. D. in Electrical Engineering with background in digital communications and signal processing. 8+ years of experience in high-speed serial link or communication system design.

The annual salary range is $126,100 - $201,500 CAD. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time.

We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals.

Ciena is anEqual Opportunity Employer, including disability and protected veteran status.

📌 Principal Serdes System/Dsp Design Engineer (Ottawa)
🏢 Ciena
📍 Ottawa