Validate Backplane Ethernet, PCIe, SATA, and USB SERDES at Synopsys from Markham or Mississauga.
As a senior ASIC verification engineer, you will help deliver mixed-signal designs through test planning, functional testing, and performance validation. The position combines Verilog, System Verilog, UVM, VMM, assertions, and coverage-driven verification.
Collaboration with digital and analog engineers is central to the work.
Key Responsibilities:
Verify current and next-generation SERDES products
Plan functional and performance testing for test chips and products
Build constrained-random and coverage-driven verification settings
Analyze functional, code, and assertion coverage
Debug complex testbench and design-related issues
Requirements:
BS or MS in Electronics, Electrical Engineering, or related discipline
8+ years of digital verification methodology experience
Solid Verilog and System Verilog test case development experience
Solid understanding of digital circuit design
System Verilog Assertions or formal verification knowledge is desired
Use SERDES verification, mixed-signal collaboration, and coverage expertise to support Synopsys connectivity products.
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