Shape semiconductor interconnect designs with high-speed layout expertise, advanced EDA tools, and wafer-level technologies at Semtech Corporation.

As a Package and PCB Layout Engineer, you will contribute to the Signal Integrity Products business unit’s R&D; hardware design community. Your focus may span multilayer substrates, carrier layouts, wafer redistribution layers, and wafer reconstruction technologies. The work supports creative designs across wide-ranging interconnect technologies.

Key Responsibilities:
Assess package feasibility with signal integrity experts
Create substrate and carrier layouts for advanced IC configurations
Develop wafer-level interconnect layouts using reconstruction technologies




Apply layout expertise across high-speed interconnect technologies
Coordinate activities with suppliers and cross-functional teams

Requirements:
Bachelor’s degree in engineering, physics, or related field
Five years’ experience in high-speed package or PCB layout
Advanced knowledge of Cadence APD and Allegro desired
Understanding of RF, analog, and digital circuits
Knowledge of mechanical, thermal, and optical design

Bring semiconductor layout experience, wafer-level interconnect knowledge, and high-speed design skills to Semtech’s R&D; team.

📌 High Speed Semiconductor Package Layout Engineer Burlington
🏢 Semtech
📍 Burlington