Senior Asic Verification Engineer — Uvm & Systemverilog - $129,600 - $179,600 A Year (Markham)

Senior Asic Verification Engineer — Uvm & Systemverilog - $129,600 - $179,600 A Year (Markham)

09 Nov
|
Qualcomm Canada
|
Markham

09 Nov

Qualcomm Canada

Markham

Develops world-class ML hardware solutions as an ASIC design verification engineer. Builds verification environments in UVM/SystemVerilog, writes tests, and develops C reference models.

📌 Senior Asic Verification Engineer — Uvm & Systemverilog - $129,600 - $179,600 A Year (Markham)
🏢 Qualcomm Canada
📍 Markham

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