Lead digital design and static timing analysis at Microchip Technology for advanced optical networking integrated circuits and connectivity solutions. Work across block and full-chip levels.
As a Principal Engineer on Microchip’s Communications Business Unit Product Development team, you will lead digital design, DFT, physical implementation, and STA. You will support the semiconductor R&D; lifecycle from concept through production release. The work uses Cadence and Synopsys synthesis suites across advanced technology nodes.
Key Responsibilities: Develop macro constraints, RAM generations, and flow configurations
Own STA signoff across multiple modes and corners
Develop and understand RTL synthesis flows and methodologies
Coordinate constraints and deliverables with RTL and DFT engineers




Ensure netlist quality through CLP, LEC, and tool checks
Requirements: Bachelor’s or graduate degree in computer, electrical, electronics, or VLSI engineering
Ten years’ synthesis, STA, and formal verification experience
Solid TCL, Perl, or Python coding and scripting skills
RTL design, UPF or CPF, and SoC STA signoff experience
Sixteen-nanometer-or-smaller tapeout experience on one or more projects
Apply digital design, synthesis, DFT, and timing expertise to Microchip’s advanced networking silicon development programs.

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📌 Principal Digital Design Engineer (Saskatchewan)
🏢 Microchip Technology
📍 Saskatchewan