Build RTL and verification expertise at Toronto-based StarIC, supporting hybrid digital IC development from modeling through gate-level simulation. Work across mixed-signal designs.

This senior engineering position covers digital blocks and ICs from initial concept, architecture, and specification through final verification. You will use VHDL or Verilog, front-end tools, simulators, synthesis, static timing analysis, back-annotation, and gate-level simulation. Responsibilities also include vector generation, lab testing, documentation, and incremental maintenance of digital designs, test systems, software, and scripts.

Key Responsibilities:

- Define architectures and specifications for digital IC blocks
- Develop RTL models and verification environments
- Perform synthesis, timing closure,



and gate-level simulation
- Generate vectors and support lab testing
- Document designs and execute incremental maintenance updates

Requirements:

- BSc or MSc in Electronic Engineering or Computer Engineering
- Three to six years of digital IC design experience
- VHDL or Verilog design and simulation experience
- Synopsys, Cadence, or Mentor front-end flow experience
- Hands-on csh, Tcl/Tk, or Perl scripting experience

Bring RTL, verification, synthesis, simulation, and scripting capabilities to StarIC’s digital integrated circuit development work.

📌 Digital ASIC Verification And RTL Engineer (Toronto)
🏢 StarIC
📍 Toronto