High speed SerDes verification needs SystemVerilog and UVM expertise at Qualcomm Canada ULC. Help validate connectivity for modern AI data centers.

This Senior Verification Engineer supports the HSI Digital Design Verification team, specializing in SerDes technology and reliable high bandwidth communication. You will review specifications, create verification plans, and develop testbenches for digital designs. Responsibilities include analog model integration, MATLAB bit matching, Ethernet and PCIe compliance testing, and simulation debug. The position also involves collaboration across Design, Systems, Firmware, and Analog teams.

Key Responsibilities:

- Devise verification plans from digital design specifications
- Build testbenches and constrained random test cases




- Facilitate bit matching between RTL and MATLAB models
- Integrate VIPs for Ethernet and PCIe compliance testing
- Collaborate on issues and achieve verification closure

Requirements:

- Master’s degree and one-plus year of relevant ASIC experience
- Solid SystemVerilog and UVM verification environment experience
- SerDes, DSP, or mixed signal verification experience preferred
- Exposure to formal, gate level, and UPF verification
- Strong communication, planning, and debugging skills

Bring SerDes, mixed signal, SystemVerilog, and UVM verification skills to Qualcomm’s connectivity engineering work.

📌 SerDes Digital Design Verification Engineer (Toronto)
🏢 Qualcomm
📍 Toronto