Advance 3nm-and-below STA and design closure at Cadence through deep timing expertise, flow customization, and technical influence.

This architect focuses on advanced-node signoff and closure solutions spanning digital design, ECOs, constraints, UPF, hierarchical STA, and 3DIC design. You will lead complex benchmarks, customize flows with scripting, and guide customer adoption across 5nm-and-below technologies. Collaboration with R&D; and Product Engineering informs tool enhancements.

Key Responsibilities:

- Lead advanced-node benchmarks and timing closure flow optimizations
- Guide customer adoption of signoff and AgenticAI capabilities
- Deploy methodologies for STA, IR Drop, and power closure
- Collaborate with R&D; and Product Engineering teams




- Position Cadence through technical industry presentations

Requirements:

- 15+ years in IC design implementation and signoff
- Deep expertise in 3nm-and-below STA and ECOs
- Experience debugging UPF and constraints across complex designs
- Solid Tcl, Python, Perl, and flow customization proficiency
- Proven executive-level customer success and technical team leadership

Use advanced-node STA, closure methodologies, and scripting expertise to solve complex Cadence customer design challenges.

📌 Advanced Node STA Architect (Toronto)
🏢 Cadence
📍 Toronto