Company Qualcomm Technologies, Inc.
Job Area Engineering Group, Engineering Group ASICS Engineering General SummaryAbout the Team Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre
- and post-silicon phases . This role focuses on content quality, validation frameworks, and system-level validation enablement , offering deep exposure to Qualcomm SoCs through bare-metal validation content , scalable automation frameworks, and complex system debug. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content , ensuring high-quality silicon validation across a wide range of SoC domains. Data center Role Summary We are seeking a highly experienced SVE Content Lead to drive validation strategy, test planning, content development, and execution for next-generation Premium Tier Mobile and AI accelerator platforms. This role owns end-to-end system-level validation content across emulation and silicon phases while partnering with Architecture, Design, DV, Software, Performance, Power, and Product teams to ensure comprehensive coverage and successful product execution. The ideal candidate combines strong SoC architecture knowledge, validation expertise, technical leadership, and program management skills to lead geographically distributed engineering teams and deliver high-quality validation solutions at scale.

Key Responsibilities
Validation Strategy & Planning Identify high-risk customer use cases and translate them into executable validation content. Define stress, power, performance, scalability, and corner-case validation scenarios. Drive coverage closure based on previous program learnings and emerging architectural risks.



Content Leadership Own end-to-end content strategy, roadmap, execution, readiness reviews, and delivery milestones. Drive content architecture and test plan reviews across multiple subsystem domains. Ensure content quality, scalability, reusability, and maintainability. Lead content stabilization, qualification, and regression activities. Drive system-level content releases for HVV, SLT, and production screening environments. Technical Leadership Partner with Architecture, Design, DV, Firmware, and Software teams to define validation requirements. Lead debug of complex silicon, emulation, firmware, and software issues. Drive root-cause analysis and corrective action plans for critical product issues. Drive cross-functional execution across multiple global sites. Coordinate content scrums, program reviews, readiness assessments, and milestone tracking. Manage external dependencies and risk mitigation plans. Provide regular executive-level status updates and technical reviews. Mentor senior engineers and future technical leaders. Build high-performing global content teams. Drive engineering excellence, execution rigor, and scalable operating models. Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field. ~8+ years of experience in SoC validation, bring-up, architecture validation, firmware, or system software.



~ Interconnects and NoC ~ Robust debugging and root-cause analysis skills. Demonstrated technical leadership across geographically distributed teams. Experience leading validation for flagship mobile, compute, AI, automotive, or server-class SoCs. Expertise in system-level content development and validation frameworks. Knowledge of performance, power, reliability, and production-screening methodologies. Experience leveraging automation, analytics, and AI-based engineering productivity solutions. This role provides the opportunity to shape validation strategy for industry-leading Snapdragon platforms while influencing architecture, methodology, AI-driven validation workflows, and next-generation silicon products across multiple business units. Bachelor’s degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. Master’s degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. Doctor of Philosophy (PhD) in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.
Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabili

📌 Responsable Planning Validations H/F (Markham)
🏢 QUALCOMM
📍 Markham