Lead complex AMD ASIC IP integration with PCIe, power-aware flows, automation, and cross-functional technical direction.
As an ASIC Design Engineer, PCIe IP Enablement, you will own complex digital IP or subsystem work from architecture through tape-out. Your responsibilities span PCIe integration, RTL implementation, low-power design, flow development, and front-to-back execution. You will also support technical decisions and mentor engineers.
Key Responsibilities: Lead AMD PCIe IP integration and SoC implementation
Drive flow development, automation, and scripting
Analyze complex problems and summarize solution options
Coordinate technical and schedule discussions across sites
Collaborate with IP, Physical Design, and SoC teams
Requirements: End-to-end ownership of complex ASIC IP or subsystems
Experience with integration, implementation, and version control
Knowledge of UPF or CPF power-aware design flows
Familiarity with tile flow, repeaters, SRAM, ECO, and DFx
Bachelor's or Master's degree in Electrical or Computer Engineering preferred
Combine ASIC ownership, PCIe integration, automation, and low-power expertise while directing high-quality AMD design execution.

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📌 Senior ASIC IP Integration Engineer (Ontario)
🏢 Advanced Micro Devices
📍 Ontario