In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements. In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements. You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon. Develop and implement power reduction strategies across SoC/IP design.
Perform synthesis and static timing analysis (STA) to achieve PPA targets.
Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
Build test plan documentation, accounting for interactions with other features, the hardware. In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements. You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. With strong analytical skills and a methodical approach, you are eager to learn, share knowledge,



and contribute to building cutting-edge silicon. Develop and implement power reduction strategies across SoC/IP design.
Perform synthesis and static timing analysis (STA) to achieve PPA targets.
Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
Build test plan documentation, accounting for interactions with other features, the hardware. Strong background in ASIC synthesis and static timing analysis (STA).
Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists, or equivalent.
Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
Knowledge of low-power design methodologies and trade-offs.
Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
Experienced with Verilog, System Verilog, C, and C++Graphics pipeline knowledgeAutomating workflows in a distributed compute setting.

About US
Tech Solutions: US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more

about US
Tech Solutions, please visit All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring. #

📌 Design Analysis Engineer (Canada)
🏢 US Tech Solutions
📍 Canada