Drive low-power ASIC design with synthesis and timing closure for complex SoC and IP projects through US Tech Solutions. Optimize PPA with industry-standard EDA tools.
This ASIC Design Engineer role focuses on digital design, power optimization, and timing closure. You will develop strategies, analyze agile and leakage power, and support reliable silicon meeting product requirements. Collaboration spans RTL design, physical design, and verification teams across time zones.

Key Responsibilities

Develop power reduction strategies across SoC and IP designsPerform synthesis and static timing analysis for PPA targetsOptimize dynamic and leakage power with EDA toolsRun UPF and CPF low-power verification checksAutomate power and timing workflowsRequirements:
Strong ASIC synthesis and static timing analysis backgroundExperience with Synopsys Design Compiler and PrimeTimeKnowledge of clock gating and power gatingUnderstanding of RTL coding with Verilog or SystemVerilogProficiency in TCL, Perl, Python, or Shell scriptingApply digital design, synthesis, and power optimization expertise to complex ASIC and SoC development with US Tech Solutions.
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📌 Low Power Asic Design Engineer (Canada)
🏢 US Tech Solutions
📍 Canada