Build silicon-proven analog IP at Synopsys using SerDes expertise, SPICE simulation, and rigorous verification methodologies. Influence scalable designs for next-generation connectivity.

As a principal-level architect, you will shape technical direction for analog macro designs and verification strategies within Synopsys’ SerDes IP portfolio. You will document methodologies, support electrical characterization, and communicate technical findings to peers and customers. Success depends on analytical problem-solving, detailed CMOS design knowledge, and readiness to lead growing teams.

Key Responsibilities

Define scalable analog architectures for SerDes IP products

Document design features, methodologies, and test plans

Consult on circuit characterization and electrical testing





Review customer-facing simulation data and technical insights

Advance design processes and verification strategies

Requirements

PhD with 10+ years or MSc with 12+ years’ experience

Silicon-proven SerDes circuit implementation experience

Knowledge of VCOs, DLLs, ADCs, DACs, and references

Experience with schematic, layout, and verification EDA tools

Solid analytical, communication, and mentoring abilities

Use analog IP architecture, SPICE analysis, documentation, and technical leadership to strengthen Synopsys SerDes products.

📌 Principal Analog IP Architect SerDes (Winnipeg)
🏢 Synopsys
📍 Winnipeg