Build silicon-proven analog IP at Synopsys using SerDes expertise, SPICE simulation, and rigorous verification methodologies. Influence scalable designs for next-generation connectivity.As a principal-level architect, you will shape technical direction for analog macro designs and verification strategies within Synopsys’ SerDes IP portfolio. You will document methodologies, support electrical characterization, and communicate technical findings to peers and customers.

Success depends on analytical problem-solving, detailed CMOS design knowledge, and readiness to lead growing teams.Key Responsibilities:

Define scalable analog architectures for SerDes IP productsDocument design features, methodologies,



and test plansConsult on circuit characterization and electrical testingReview customer-facing simulation data and technical insightsAdvance design processes and verification strategiesRequirements:

PhD with 10+ years or MSc with 12+ years’ experienceSilicon-proven SerDes circuit implementation experienceKnowledge of VCOs, DLLs, ADCs, DACs, and referencesExperience with schematic, layout, and verification EDA toolsStrong analytical, communication, and mentoring abilitiesUse analog IP architecture, SPICE analysis, documentation, and technical leadership to strengthen Synopsys SerDes products.

📌 Principal Analog Ip Architect Serdes (Winnipeg)
🏢 Synopsys
📍 Winnipeg