Principal Analog Layout Design Engineer/Lead Senior/Principal High-Speed Analog Layout Design EngineerAbout the Role Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits.

You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced setting and enjoys mentoring others while contributing directly to cutting-edge chip development. Lead and own the physical layout design of complex analog/mixed-signal macros (e.ADCs, DACs, PLLs), from floor planning through final verification Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability Mentor and guide junior layout engineers/contractors across multiple time zones,



enforcing best practices in layout design and verification Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus) Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design and their impact on circuit performance Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design Experience working in collaborative environments with international and remote teams Experience using revision control systems for layout design management Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization Proven ability to collaborate with international teams (U.The chance to play a foundational role at a high-growth semiconductor start-up A collaborative, international team culture where ideas and initiative are valued A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity #

📌 Principal Analog Layout Design Engineer/Lead (Ottawa)
🏢 CELERO COMMUNICATIONS
📍 Ottawa