Build and verify configurable FPGA IP in Toronto, applying digital logic, scripting, and simulation skills with Altera’s PACE engineering team.

As a student intern, you will contribute to RTL development and verification for PHY-lite, MIPI, and LVDS-based high-speed interfaces. The work includes advanced FPGA architectures, design examples, simulation models, and documentation integrated with Quartus Prime. You will collaborate across silicon validation, post-silicon validation, application engineering, and customer experience.

Key Responsibilities:

- Verify interfaces using methodologies, frameworks, and regression tests
- Develop verification IP and bus functional models
- Implement RTL for high-speed transmission interfaces
- Support power-on activities, debugging,



and new product releases
- Provide technical documentation and customer support

Requirements:

- Currently pursuing a related bachelor’s degree
- Three months’ experience designing or verifying digital logic hardware
- Three months’ scripting or programming experience
- Experience with SystemVerilog, Verilog, VHDL, Python, TCL, Perl, or C/C++
- Attention to detail and excellent problem-solving ability

Strengthen Altera’s high-speed interface solutions through digital logic verification, RTL development, simulation, and cooperative engineering.

📌 Digital Logic Verification Intern (Toronto)
🏢 Altera
📍 Toronto