Drive low-power ASIC design with synthesis and timing closure for complex SoC and IP projects through US Tech Solutions. Optimize PPA with industry-standard EDA tools.

This ASIC Design Engineer role focuses on digital design, power optimization, and timing closure. You will develop strategies, analyze dynamic and leakage power, and support reliable silicon meeting product requirements. Collaboration spans RTL design, physical design, and verification teams across time zones.

Key Responsibilities:

- Develop power reduction strategies across SoC and IP designs
- Perform synthesis and static timing analysis for PPA targets
- Optimize dynamic and leakage power with EDA tools
- Run UPF and CPF low-power verification checks
- Automate power and timing workflows

Requirements:

- Solid ASIC synthesis and static timing analysis background
- Experience with Synopsys Design Compiler and PrimeTime
- Knowledge of clock gating and power gating
- Understanding of RTL coding with Verilog or SystemVerilog
- Proficiency in TCL, Perl, Python, or Shell scripting

Apply digital design, synthesis, and power optimization expertise to complex ASIC and SoC development with US Tech Solutions.

📌 Low Power ASIC Design Engineer (Markham)
🏢 US Tech Solutions
📍 Markham