Lead RTL verification with Cadence in Montreal, applying SystemVerilog and reusable environments to high-performance physical IP development. This full time role requires office work.

As Lead Verification Engineer, you will verify digital RTL and develop reusable verification components and environments. You will contribute to flow development, test planning, execution, functional coverage closure, and code coverage closure. Collaboration spans design, verification, project management, and digital and analog teams.

Key Responsibilities:

- Verify digital RTL for industry-standard protocol physical IP
- Develop reusable verification components and environments
- Develop verification flows and test plans
- Execute tests and close functional coverage




- Communicate project progress across technical teams

Requirements:

- Bachelor's degree in electrical, computer engineering, or computer science
- Understanding of verification architecture, methodologies, and Metric Driven Verification
- Knowledge of UVM and SystemVerilog Assertions
- Understanding of digital design flow and coverage planning
- Ability to communicate in English

Apply digital verification, SystemVerilog, coverage, and collaboration skills to Cadence physical IP projects in Montreal.

📌 Lead RTL Verification Engineer (Montreal)
🏢 Cadence Design Systems
📍 Montreal