Are you passionate about cutting-edge semiconductor and high-speed interface technologies? We are looking for a Design Verification (DV) Engineer with strong expertise in SystemVerilog (SV), UVM, and PCIe verification to join a dynamic engineering team.

Key Responsibilities:

- Design and develop robust verification environments using SystemVerilog and UVM
- Verify PCIe Gen3/Gen4/Gen5 protocols and ensure compliance with specifications
- Develop reusable verification components, testbenches, and methodologies
- Create and maintain assertions (SVA), coverage models, and constrained-random test scenarios
- Debug complex design and protocol issues and drive them to closure
- Collaborate closely with design and architecture teams

Required Skills:





- Solid experience in Design Verification using SystemVerilog (SV) and UVM
- Hands-on experience in PCIe Gen3/Gen4/Gen5 protocol verification
- Strong understanding of:
- LTSSM
- Data Link Layer
- Physical Layer
- Exposure to AXI, APB, and AHB protocols
- Experience developing reusable verification environments and VIPs
- Knowledge of SVA, coverage-driven verification, and constrained-random methodologies
- Experience with simulators such as VCS, Xcelium, or Questa
- Excellent debugging, analytical, and problem-solving skills

📌 Design Verification Engineer (Canada)
🏢 HCLTech
📍 Canada