Drive low-power ASIC design, synthesis, and timing closure for complex SoC and IP designs supporting advanced semiconductor products.

This ASIC Design Engineer develops power reduction strategies and optimizes power, performance, and area. The work includes static timing analysis, low-power verification, and workflow automation. Collaboration spans RTL design, physical design, and verification teams across time zones.

Key Responsibilities:

- Develop power reduction strategies across SoC and IP designs
- Perform synthesis and static timing analysis for PPA targets
- Optimize agile and leakage power using EDA tools
- Run UPF and CPF power intent verification checks
- Support lint, CDC, timing, and power sign-off activities

Requirements:

- Strong ASIC synthesis and static timing analysis background
- Experience with Synopsys Design Compiler and PrimeTime
- Knowledge of clock gating, multi-Vt, and power gating
- Familiarity with UPF and CPF specifications
- Verilog, SystemVerilog, and scripting proficiency

Apply ASIC synthesis, power optimization, timing closure, and verification expertise to complex semiconductor SoC and IP designs.

📌 Low Power ASIC Design Engineer (Vaughan)
🏢 TekWissen
📍 Vaughan