Digital Design & Verification (RTL + UVM + Microarchitecture)Job Description: Senior Digital Design & Verification EngineerWe are searching for Senior Digital Engineers with solid RTL and Verification expertise to join a deep-tech compute architecture team. The role involves hybrid responsibilities across microarchitecture, RTL development, DV environments and subsystem integration.ResponsibilitiesDevelop RTL for compute subsystems, controllers, datapaths and interfacesContribute to microarchitecture definition and technical reviewsBuild UVM-based verification environments and test plansDrive functional coverage, constrained-random testing and debugSupport FPGA bring‑up and silicon validation activitiesCollaborate with physical design, architecture and mixed-signal teamsRequirementsStrong background in RTL coding (SystemVerilog/Verilog)Solid experience with UVM and modern DV methodologiesKnowledge of SoC integration, buses, protocols (AXI/APB)Exposure to FPGA, DFT, CDC/RDC, linting and subsystem verificationAbility to work across design + verification flows with technical ownershipLocationZurichSalary120.000 €#J-18808-Ljbffr

📌 Digital Design & Verification - €120.000 A Year (Winnipeg)
🏢 Botic Partners
📍 Winnipeg