ASIC verification specialists can shape robust UVM environments for NVIDIA Tegra SoC IP, focusing on complex coherent interconnect and system interfaces.
This Senior Verification Engineer position supports the Tegra SoC IP Verification team and High Speed Coherent Interconnect Hub IP. You will define test plans, develop verification infrastructure, and verify protocol compliance across complex interfaces. Collaboration spans architecture, design, FPGA, emulation, software, and post-silicon teams.
Key Responsibilities
Maintain constrained-random verification infrastructure and testbenchesComplete plans covering protocol compliance and key IP featuresDebug RTL and verification issues with architecture and design teamsSupport system validation and silicon bring-up activitiesDrive functional and code coverage toward signoffRequirements: Three-plus years of complex ASIC verification experienceStrong SystemVerilog and UVM methodology knowledgeExperience with constrained-random and coverage-driven verificationExperience creating checkers, assertions, and functional coverageStrong problem-solving skills with simulation and debug toolsBring ASIC verification, UVM infrastructure, protocol analysis, and cross-functional debugging skills to NVIDIA’s Tegra interconnect programs. #J-18808-Ljbffr