Drive AMD IP validation across Markham or Vancouver, applying digital design, ASIC debug, and scripting skills to complex SOC programs. Collaborate across teams and locations.
As an IP Validation Design Engineer on AMD’s NBIO Team, you will plan, validate, and debug hardware IP for APU, CPU, Compute, and Discrete Graphics SOC programs. The work combines functional validation strategy, pre-silicon shift-left activities, and post-silicon investigation. You will collaborate with Design Verification, Diagnostics, Emulation, software, hardware, and customer support teams. Success requires analytical problem-solving, communication, and independent task ownership.

Key Responsibilities

Define, document, execute, and report functional validation strategiesDevelop scripts, automation, tools,



and validation methodologiesDebug IP issues through pre-silicon and production phasesSupport shift-left readiness with cross-functional engineering teamsLead technical discussions resolving issues and initiativesRequirements:
Bachelor’s or master’s degree in EE, CS, or related fieldExperience in digital design, verification, or post-silicon validationExtensive ASIC debug techniques and methodologies experienceStrong Ruby or Python scripting skillsExcellent written and verbal communication skillsApply digital validation, ASIC debug, automation, and communication expertise to AMD’s next-generation IP programs in Markham or Vancouver.
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📌 Amd Ip Validation Design Engineer (Winnipeg)
🏢 Advanced Micro Devices
📍 Winnipeg