Drive AMD IP validation across Markham or Vancouver, applying digital design, ASIC debug, and scripting skills to complex SOC programs. Collaborate across teams and locations.

As an IP Validation Design Engineer on AMD’s NBIO Team, you will plan, validate, and debug hardware IP for APU, CPU, Compute, and Discrete Graphics SOC programs. The work combines functional validation strategy, pre-silicon shift-left activities, and post-silicon investigation. You will collaborate with Design Verification, Diagnostics, Emulation, software, hardware, and customer support teams. Success requires analytical problem-solving, communication, and independent task ownership.

Key Responsibilities

Define, document, execute, and report functional validation strategies

Develop scripts, automation, tools, and validation methodologies





Debug IP issues through pre-silicon and production phases

Support shift-left readiness with cross-functional engineering teams

Lead technical discussions resolving issues and initiatives

Requirements

Bachelor’s or master’s degree in EE, CS, or related field

Experience in digital design, verification, or post-silicon validation

Extensive ASIC debug techniques and methodologies experience

Robust Ruby or Python scripting skills

Excellent written and verbal communication skills

Apply digital validation, ASIC debug, automation, and communication expertise to AMD’s next-generation IP programs in Markham or Vancouver.

📌 AMD IP Validation Design Engineer (Winnipeg)
🏢 Advanced Micro Devices
📍 Winnipeg