Develop mixed-signal timing silicon at SiTime, using AMS modeling, SystemVerilog, Verilog-A, and post-layout verification knowledge. As a Staff Analog Design Engineer, you will lead circuit blocks from specifications through proven silicon. You will work across analog and mixed-signal design flows, simulation methods, design rules, behavioral modeling, and post-layout verification. The position partners with layout, digital, system design, validation, and product development teams.

Key Responsibilities
- Develop specifications and design analog timing circuits
- Integrate circuit blocks into complete chip designs
- Collaborate with layout, digital, and system teams
- Apply simulation and verification methods during development




- Support validation, qualification, and product release

Requirements:
- Master’s or PhD in Electrical Engineering
- Six or more years of analog or mixed-signal IC design
- Proficiency with Cadence analog or mixed-signal tools
- Experience with SystemVerilog, Verilog-A, AMS, and behavioral modeling
- Familiarity with post-layout verification and analog design rules Use mixed-signal design flow, behavioral modeling, and verification skills to advance SiTime’s precision timing products.

📌 Staff Mixed Signal IC Design Engineer (Ottawa)
🏢 SiTime
📍 Ottawa