SystemVerilog and UVM verification work awaits at Synopsys in Markham or Mississauga, validating high-speed mixed-signal products.
This senior engineering position supports verification for Backplane Ethernet, PCIe, SATA, and USB SERDES products. You will work with digital and mixed-signal engineers across test planning, simulation, and product validation. The work includes constrained-random verification, coverage analysis, assertions, and debugging.
Key Responsibilities
Create and update test plans and test casesWrite modular Verilog, SystemVerilog, UVM, and VMM testbenchesDevelop SystemVerilog assertions and functional coverageMonitor regressions and debug RTL and gate-level failuresTrack issues in Jira and document findings in ConfluenceRequirements: BS or MS in Electronics, Electrical Engineering, or related fields8+ years using digital verification methodologies such as VMM or UVMExperience writing Verilog and SystemVerilog test casesKnowledge of high-speed digital and mixed-signal designFamiliarity with C/C++, RISC processors, Python, or PerlApply digital verification expertise, coverage analysis, and debugging skills to Synopsys SERDES development in Markham or Mississauga. #J-18808-Ljbffr