Build AMD PCI Express IP with RTL, Verilog HDL, and subsystem integration expertise. Drive accurate, high-quality implementation across front-to-back design flows.
This ASIC Design Engineer role focuses on PCIe IP Enablement within AMD’s design organization. You will develop digital IP from architecture through tape-out, supporting implementation, verification-related closure, and SoC deployment. Collaboration spans IP designers, Physical Design teams, and SoC leads.

Key Responsibilities

Design and implement PCIe subsystem IP for SoC integrationDrive RTL quality through lint, CDC, synthesis, LEC, and STASupport subsystem integration, ECO, SRAM generation, and repeatersAddress clocks, testing, debugging,



and design implementation needsCollaborate with multi-site engineers and managers on schedulesRequirements:
Proficiency with RTL and Verilog HDL digital designExperience with integration and implementation of IPs to SoCFamiliarity with RDC, equivalence checks, and static timing analysisUnderstanding of low-power techniques and power-aware checksElectrical Engineering or Computer Engineering degree preferredUse RTL design, PCIe subsystem integration, and closure expertise to deliver robust ASIC IP at AMD.
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📌 Asic Rtl Engineer Pci Express (Winnipeg)
🏢 AMD
📍 Winnipeg