SystemVerilog and UVM expertise drives ASIC verification at Qualcomm Canada ULC. Build reliable connectivity technology for high performance products.
As a Senior Verification Engineer, you will verify digital and analog mixed signal designs within Qualcomm’s HSI Digital Design Verification team. The team develops high speed SerDes technology for communication among compute, memory, storage, and networking components. Your work spans testbench development, simulation debugging, protocol compliance, and verification closure. Collaboration with Design, Systems, Firmware, and Analog teams supports product execution.
Key Responsibilities
Review specifications and create verification plans for design functionalityDevelop SystemVerilog and UVM testbenches and test casesDebug simulations and identify root causesIntegrate analog models and third-party protocol verification IPSupport post-silicon chip bringup and verification closureRequirements:
Bachelor’s degree and two-plus years of relevant ASIC experienceProficiency with SystemVerilog, UVM, and constrained random verificationExperience developing and maintaining verification environmentsKnowledge of Ethernet and PCIe standards is desirablePython, Perl, C/C++, and GNU Make experienceApply ASIC verification, SystemVerilog, and UVM expertise to advance SerDes connectivity at Qualcomm Canada ULC.
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