FPGA Verification Engineer

Aversan Inc. (

We are currently seeking a qualified FPGA Verification Engineer to join our team.

Job Type: Full-Time

Work Arrangement: Remote

FPGA/ASIC Design Verification Engineer

Duties

- DO-254 Airborne Electronic Hardware (AEH) development and certification process related to functional allocation, design, simulation, synthesis, place & route, test planning, verification and introduction to production.
- Utilize development process and participate in design reviews for key characteristics of performance as well as safety/reliability, test and manufacturability.
- Lead and Participate in the definition of FPGA validation and verification plans;
- Develop simulation verification test benches, verification components and bus-functional models in SystemVerilog, using standardized verification methodologies such as UVM;
- Develop and implement on-target test environments;
- Develop, document and execute test procedures, and write test reports;
- Provide documentation for requirements, design descriptions, tests and production support.
- Support management, systems and manufacturing in various planning or problem solving tasks.

Qualifications

- Bachelor in Electrical or Computer Engineering (or equivalent).
- Robust experience in designing / verifying complex digital systems.
- Experience in developing verification plans, test benches and test cases.
- Experience in HDL coding for high-speed and low power digital circuits




- Good communication skills, written and oral, and excellent interpersonal skills

Assets

- Knowledge of Modelsim/Questasim
- Knowledge of SystemVerilog and Universal Verification Methodology (UVM)
- Knowledge of ARINC, AMBA, AXI, PCIe and Ethernet busses
- Proficiency with configuration, documentation and trace tools (Microsoft Office, DOORS).

Please Note

Interested applicants must apply directly to this link to be considered for this position:

The name of the file for the resume should be the applicant’s full name and the position title you are applying for. The resume format should be PDF.

Compensation: $140,000 – $170,000 CAD (annual salary)

The base salary or rate offered to an applicant within this range is determined by considering several factors, including the individual's geographic location, skills, competencies, and unique qualifications. This ensures compensation is fair and aligned with the specific requirements and attributes of each candidate.

Vacancy Status: This posting is for an existing vacancy.

AI in Hiring: We use AI tools to assist with application management (e.g., organizing submissions and surfacing potentially relevant qualifications). AI is not used to make hiring decisions. All decisions are made by our hiring managers and recruitment team. Our use of AI is governed by security and privacy risk assessments aligned with our cybersecurity framework.

📌 FPGA/ASIC Design Verification Engineer (Montreal)
🏢 Aversan
📍 Montreal