Apply UVM and C/C++ expertise to functional verification for complex ASICs and IP cores in a combined CPU/GPU development effort. This Verification Validation Engineer role supports design verification across blocks, chips, and systems. You will work with design and verification engineers while creating simulation tests, debugging results, and applying verification methodologies. The work involves active projects and increasingly complex SoC designs. Key Responsibilities:
Functionally verify complex ASIC and IP core blocks Understand design elements across block, chip, and system contexts Document and execute directed and constrained-random test plans Apply evolving verification methodologies to complex SoC designs Use hardware modeling or assertion-based verification methods Requirements:
10+ years of verification experience on large ASIC projects Strong C/C++ development background in Linux environments Robust debugging skills with GDB and Valgrind Proficiency in object-oriented programming, STL, architecture, and data structures UVM and design verification experience, with FPGA verification acceptable Bring ASIC verification, UVM, C/C++, debugging, and analytical skills to complex CPU/GPU and SoC development.